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<zoly> hi
<Robert> Hi again.
<zoly> robert ... is there _any_ place on the net where you are not lurking?
<zoly> oh
<zoly> i just found one :)
<Robert> Far too many - I'm just in a dozen or so channels at the moment.
<zoly> there is no robert on #coders :)
<Robert> Is it worth changing that?
<zoly> 3 ppl on channel
<archivist_> nearly as bad as ***embler
<zoly> nobody answering my initial "hi"
<Robert> Hehe.
<zoly> oh. actually, just 2
<zoly> plus chanserv
<Robert> No coders on freenode? That's hard to believe.
<Julian> Hi zoly
<zoly> hi, Julian
<imaginator> zoly: you're supposed to wait 3-8 business days
<zoly> imaginator: i have 24 h dsl disconnect
<drocon> hmm
<drocon> i have a question
<drocon> do CISCs have any advantage over a RISC nowadays
<drocon> like how would x86 pair up with a ppc
<xark> drocon: The lines are very blurred these days.
<xark> drocon: For example, modern CISC internally converts to RISC-like ops. So in effect, CISC chips are RISC chips with a fancy "decompressing decoder" stage (CISC does generally have better code density)
<xark> Similarly, most RISC chips have a few CISCy opcodes (i.e., FPU stuff isn't single cycle etc.)
<xark> drocon: However, I think transistor vs transistor RISC is generally better (i.e., complex CISC chips get pretty good performance vs RISC - but generally consume more transistors in the complexity [that could be used for more cache on RISC]).).
<drocon> ah
<drocon> cool :) thanks
<Charlls> heyo
<Charlls> in x86, we have the stack which holds the frame data; return address + argument data + local vars, correct?
<Charlls> and the heap holds dynamically allocated data right?
<aFlag> hi
<aFlag> i hear that linux kernel uses some interrupt for making context switch. How that works? there's something you p*** to the processor and it saves all the registers in the memory somewhere?
<xark> aFlag: Something like that. Pretty much all preemptive tasking systems use an interrupt (what else will preempt :).
<xark> multi-tasking*
<xark> Charlls: Yes, but understand there is little distinction to the CPU (just different areas of main memory).
<Charlls> i see
<xark> Charlls: The "stack" is whatever area of memory is pointed to by the stack pointer.
<Charlls> in general can you think of an architecture that needs more than a stack? or this is some completely OS-dependant?
<xark> Charlls: Very often there are multiple stacks.
<xark> Charlls: Typically there are "user" stacks for application use, and kernel (or system) stacks for use by various interrupts and kernel functions.
<xark> Charlls: Some CPUs have the concept of different stacks, and sometimes its the OS that does this (or both).
<xark> [The OS can easily switch around the stack pointer to provide multiple stacks to different tasks].
<Charlls> hmm.. would u say it is right to ***ume the stack is more or less always an implementation of a functional hierarchy?
<Charlls> like funcA which calls B and C, stacks gets pushed with funcA frame, then funcB frame gets pushed, then pops then funcC...
<xark> Charlls: Well, I would say its an area of memory used for temporary storage and always increments or decrements to allocate or free memory. How its used is very up to the app and OS.
<xark> (and CPU).
<Charlls> ok
<Charlls> thanks for the clarification
<xark> Charlls: Several common CPUs don't even use the CPU for subroutine calls (at least directly, they have a return address register and its up to code to push it on a stack if needed).
<xark> er, don't even use the stack for subroutine calls...
<Charlls> i understood
<Charlls> bye
<igor47> question: is this legal, or i have to use an intermediate register?: leal (%ecx,%ebx,1),(%edx) (i need ecx + ebx -> M(%edx) )
<prolific> I don't think you can use two memory locations with leal
<igor47> well, the first is not really a memory address, its just an addition
<igor47> i know i can't read from two addresses in one instruction, but the first part of that just does the calculation...
<prolific> () = indirection
<igor47> not for leal, though, right? that first part won't actually read the memory address, it'll just load what it calculates to be it into the destination
<prolific> Well, it takes the address of whatever (x+y) points to
<igor47> can a single instruction access one register twice? i'm trying to do: movl %eax, (%eax)
<meow`> yup
<patrik> Do you guys know if normal C compilers sometimes jump to functions with a jump instruction instead of a call?
<Goplat> sure, if it'
<Goplat> if the call is the last thing done in the function
<patrik> Hmm, not sure I understand
<patrik> Im trying to identify the locations of the functions from a binary
<Goplat> if you have> void foo() { blah; blah; blah; bar(); } the foo function can just end with "jmp _bar", and then when bar returns it will return to where foo was called from
<xark> patrik: There is an optimazition called "tail recursion elimination" where when code calls a function that calls another function right before a return converts the 2nd call into a jump.
<patrik> Oh I see.
<xark> patrik: Not real common, but very possible.
<Goplat> tail recursion is when a function calls itself at the end
<Goplat> not another function... but same idea
<patrik> Yes I've read about tail recursion.
<patrik> But looking for locations where call functions point is a good start to find the entry points to some of the functions, right?
<xark> OK, do you remember what this optimization is called (tail something IIRC).
<xark> ?
<patrik> No I don't
<xark> Ahh. Gcc lists "Tail call eliminiation" as an optimization is performs. I think that is it.
<xark> it
<patrik> sounds like it could be
<xark> Yeah. Makes more sense than "recusion" in this case (gcc also lists that optimization).
<xark> recursion*
<patrik> Do you know at which optimization level gcc does this?
<HanzZ> hi... i try programming with ***embler in C, but i have error "Error: too many memory references for `mov'"
<HanzZ> it is simply mov => "mov ecs, cx \n\t"
<HanzZ> what is wrong?
<Robert> There's no "ecs" register.
<Robert> What are you trying to do?
<Robert> For the record, some languages rely heavily on tail recursion.
<Robert> I think that in some Forth systems, it's the ONLY looping construct.
<Robert> And in practice, many functional languages use it a lot as well.
<Robert> But I guess I'm leaving the subject here.
<Robert> -foptimize-sibling-calls
<Robert> Optimize sibling and tail recursive calls.
<Robert> Enabled at levels -O2, -O3, -Os.
<Robert> patrik: (from the gcc man page)
<Robert> Line 3299 in my system. So it's understandable if you didn't find it. ;)
<HanzZ> Robert: how can i mov something to AH register?
<Robert> mov ah,something
<Robert> But note that "something" should be 8-bit.
<HanzZ> i know
<Robert> "mov ah,cx" won't work, for example.
<Robert> OK.
<HanzZ> hmm
<HanzZ> Robert: and 02h == 0x02 ?
<Robert> Yes.
<Robert> Or possibly 2am ;)
<HanzZ> iam cool ;D
<HanzZ> sorry
<Robert> Heh.
<HanzZ> bad terminal ;)
<patrik> Robert, tackar
<HanzZ> Robert: and how can i mov ah (or cx etc...) to the C++ variable?
<HanzZ> do you know this?
<HanzZ> ;)
<Robert> Er...
<Robert> That depends. Is it a normal global variable?
<Robert> In that case mov [myvariable],ah should work.
<patrik> HanzZ, if you're using gcc. Take a look at http://www.ibiblio.org/gferg/ldp/GCC-Inline-***embly-HOWTO.html
<Robert> I was ***uming NASM/YASM/FASM syntax here, actually. But yeah, listen to patrik if you want to use inline asm with gcc.
<HanzZ> Robert: I am using gcc, of course ;)
<Robert> gcc...16-bit...
<HanzZ> ;)
<HanzZ> patrik: only one things... how can i mov dh to the variable... i tried this one hour ;( thanks
<HanzZ> ?
<HanzZ> *thing
<joshux> if I want to write C 16bit library in asm
<joshux> do I have to write different code for different memory model?
<wobster> joshux, at least you should take great care of what your're doing
<Robert> Writing a 16-bit library in 2005, is that what you want to do?
<joshux> ic , at least how many code I have to write if I want to take care of each model
<Robert> If it's just for fun/homework, you would probably just want to consider one model.
<wobster> with "take care" I meant, that you should be very aware of the segmentation if you plan to do anything "big" in old pc-days scales
<DarKPhoeniX> plop
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